synopsys 職缺
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- 聯發科技新竹市Synopsys Verdi. 4. Experience with Synopsys PrimeTime. 5. Experience with Synopsys NanoTime...
- TSMC台灣EDA vendors: Ansys, Cadence, Mentor, and Synopsys. 3. Good programing skills... C++, Python...
- INTEL新竹市algorithm development. Specific experience with Synopsys ICV... Siemens Calibre. Background...
- Synopsys新竹市Synopsys is seeking a dynamic and experienced Senior Sales Manager to drive the sales of our entire...
- INTEL新竹市following EDA tools: -Siemens Calibre -Synopsys ICV -Cadence Pegasus Inside this Business Group...
- Marvell新竹市learn in Cadence Virtuoso VXL... Synopsys “Custom Compiler” layout tools. Experienced in Mentor...
- Marvell新竹市skills: Logic or physical synthesis using Synopsys or Cadence tools, DFT generation and verification...
- Synopsys新竹市About Us: At Synopsys, we are dedicated to innovating and delivering top-notch hardware products...
- Marvell新竹市CALIBRE DRC, ERC, LVS reports. Proficient in Synopsys or CADENCE layout entry tools; programming...
- Synopsys新竹市work with Synopsys’ customers... demos Provide feedback to Synopsys R&D for continuous IIP product...
- Synopsys新竹市promote Synopsys solutions... produce differentiated Synopsys results in addressing customer...
- TSMC台灣capability. 3. Expertise in Cadence Innovus... Synopsys ICC2. 4. Experience in block level place...
- NVIDIA新竹市Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC...
- Synopsys新竹市product specialist to drive the success of Synopsys physical design flow and tools focusing on IC...
- Synopsys新竹市Job Description for MSAM (Manufacturing Solutions Account Manager... develop and grow accounts...
Job Post Details
地點
新竹市
完整職缺描述
1. 根據電源管理晶片 (PMIC) 類比電路的行為提供行為模型 (Verilog Format) 2. 根據電源管理晶片 (PMIC) 系統需求提供驗證場景和執行驗證計畫 3. 根據驗證需求使用可能的技術，如Constrained-Random Verification(CRV), SystemVerilog UVM, SVA, power aware simulation 或是 formal equivalence checking)
1. Proficiency in Verilog language. 2. Experience with Synopsys VCS. 3. Experience with Synopsys Verdi. 4. Experience with Synopsys PrimeTime. 5. Experience with Synopsys NanoTime is a plus. 6. Experience with Perl/TCL scripting is a plus. 7. Experience with SystemVerilog is a plus. 8. Experience with UVM (Universal Verification Methodology) is a plus. 9. Experience with Cadence/Synopsys AMS (Analog/Mixed-Signal) platform is a plus. 10. Familiarity with Analog design flow is a plus.
1. Proficiency in Verilog language. 2. Experience with Synopsys VCS. 3. Experience with Synopsys Verdi. 4. Experience with Synopsys PrimeTime. 5. Experience with Synopsys NanoTime is a plus. 6. Experience with Perl/TCL scripting is a plus. 7. Experience with SystemVerilog is a plus. 8. Experience with UVM (Universal Verification Methodology) is a plus. 9. Experience with Cadence/Synopsys AMS (Analog/Mixed-Signal) platform is a plus. 10. Familiarity with Analog design flow is a plus.
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